Prior Art PCI-CardBus Footprint Background
There are several problems associated with the de-facto-standard PCI-CardBus footprints. One of the first-to-market PCI-CardBus controllers was brought to market in a 144-pin package, and was introduced by Texas Instruments in the 1997 timeframe, known as the PCI1210. It was a widely adopted product that bridges a PCI Local bus to a single PC Card socket enhanced with the 32-bit CardBus protocol. Texas Instruments also introduced a product that bridges a PCI Local bus to two independent dual PC Card sockets enhanced with the 32-bit CardBus protocol. This product, the PCI1130, was introduced in a 208-pin package, and was also widely adopted. The 208-pins accommodate the PCI signals, and two sets of signals specified by the PC Card Standard to allow for simultaneous operation of the two PC Card sockets.
Several companies developed products that are pin-compatible to the PCI1210, including Texas Instruments. TI's PCI1410 is pin-compatible, O2 Micro's OZ6912 is pin-compatible, Ricoh's R5C475 is pin-compatible, and most recently introduced ENE's CB1410 is pin-compatible. Millions of chips in this package footprint are sold each year to notebook computers and other PC Card enabled systems, and is well understood in the industry that TI introduced the de-facto-standard PCI-CardBus footprint and others followed.
As Texas Instruments rolls out new technology in the PCI1510 PCI-CardBus controller, it retains a high level of pin-compatibility with the de-facto-standard PCI1410 footprint, as set forth in the data manual for this part.
The concept of utilizing 208-pin packaging to provide simultaneous operation of the two PC Card sockets was also widely adopted. Texas Instruments continues this legacy with the new introduction of the PCI1520, and competitors including Ricoh, O2Micro, and ENE all provide simultaneous PC Card socket operations utilizing two sets of signals specified by the PC Card Standard.
Prior-Art Solution to Board Space Problem
Mini-PCI environments are often very board area constrained, as they are often used for mobile products that need to be small and light (e.g. notebook computers). The de-facto standard 144-pin package is 20 mm×20 mm in a QFP footprint and 13 mm×13 mm in the mBGA footprint. The mechanical differences between QFP and mBGA are provided in the PCI-CardBus data manuals. There is a significant cost delta between QFP and mBGA packages, due to materials, assembly, test fixtures, production volume, and other factors; however, several Mini-PCI systems implement the mBGA package for board savings and sacrifice the cost advantage of the QFP. However, the added expense on packaging provides no real functional value to the system.
The identical trade-off is made for 208-pin packaged dual socket PCI-CardBus bridge devices. The 208-pin package is 30 mm×30 mm in a QFP footprint, and 16 mm×16 mm in the mBGA footprint. Most Mini-PCI systems cannot accommodate the 208-pin QFP footprint, and it is very rare that a Mini-PCI system utilizes the 208-pin QFP. Instead, the added expense is typically made to utilize the 208-pin mBGA footprint, and no additional value other than board area is gained with this expense.
Prior-Art Solution to IO Leakage Problem
Mobile products that implement Mini-PCI are often equipped with a battery, and power consumption is therefore a critical concern. Several power management techniques have been implemented to reduce power consumption, many of which provide the option to remove PCI bus power. If any device signals connected to the PCI bus remain powered when the PCI bus power has been removed, there is a high possibility of leakage through those terminals. Leakage is getting to be a big concern in this industry, internal leakage and external leakage, as pointed out by Intel's leader Andrew Groves in a Wall Street Journal article Dec. 11, 2002.
Some of the multi-function terminals on the de-facto 144-pin package (typically named MFUNC6:0 or MF6:0 located at QFP terminals 60, 61, 64, 65, 67, 68, and 69) are used for PCI functions, such as interrupt signaling, exclusive access control via LOCK#, and PCI clock control. When configured for these PCI functions, it is desirable from a leakage standpoint to power them off when the PCI bus power is removed.
Terminals are typically grouped by IO power requirements. Two adjacent terminals with different power requirements delimit the groupings. The reason IOs are grouped by power requirements is to limit the number of IO power rings that are needed to route bus power to the IO cells around a chip. Adding more IO power rings increases die area and increases cost. The de-facto 144-pin package makes it difficult as the multi-function terminals are in a different grouping than the PCI terminals. The PME# signal located at the de-factor 144-pin location 59 is defined by the PCI Power Management specification as a signal that requires power when PCI power is removed. Thus, a grouping ends between pin 57 (PCI Powered Address/Data Signal AD0) and pin 59.
One prior art solution to this IO leakage problem, as illustrated in FIG. 1, is to add an IO power ring to bring both auxiliary power to the PME# signal and to provide the PCI power to signals routed to MFUNC terminals.
FIG. 1 shows a conventional method of providing two separate power sources to input/output cells in a chip that need different voltage levels, and are not cleanly grouped such that one power rail can be split into groups. PCI IOs 1, 2, and 3 (101, 102, 103) all need power from PCI VCC power supply 100. An IO cell 104 that requires power from an auxiliary power source 105 separates the PCI IOs. The addition of AUX VCC 105 can cause chip area to increase, and increase the cost of the chip.